FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC

Vincent Andrew Akpan; Dimitrios Chasapis; George Dimitriou Hassapis

doi:doi:10.11648/j.ajesa.20220902.11

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FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC

Vincent Andrew Akpan, Dimitrios Chasapis, George Dimitriou Hassapis

Published in American Journal of Embedded Systems and Applications (Volume 9, Issue 2)

Received: 10 May 2022 Accepted: 9 June 2022 Published: 8 September 2022

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Abstract

The computational overload involved in the implementation of nonlinear model predictive control (NMPC) cannot be over-emphasized due to the double optimizations involved for the nonlinear model identification phase as well as the NMPC controller design phase. The computational burden becomes more time-critical for constrained multivariable control systems with relatively short sampling time. This paper presents a novel and comprehensive model-based design (MBD) approach for real-time closed-loop implementation of a version of NMPC referred here as adaptive generalized predictive control algorithmic co-processor (AGPC algorithmic co-processor) integrated with a well-designed embedded PowerPC™440 processor core on Virtex-5 FX70T ML507 FPGA (field programmable gate array) for the auto-pilot control of a nonlinear F-16 aircraft with a sampling time of 0.5 second. The result shows that the real-time closed-loop implementation of the neural network identification and the AGPC algorithms on the FPGA with embedded PowerPC™440 processor combined with an AGPC algorithmic co-processor at each sampling time is accomplished within 0.16502 microseconds (μs) when compared to the 6.1048 seconds obtained using Intel® Core™2 CPU personal computer for the control of the auto-pilot unit of a nonlinear F-16 aircraft. The demonstrated and validated model-based FPGA implementation techniques can be adapted and deployed for the real-time control of multivariable control systems having relatively short sampling time. The computation time and FPGA device utilization at each stage of the MBD implementation are also presented.

Published in	American Journal of Embedded Systems and Applications (Volume 9, Issue 2)
DOI	10.11648/j.ajesa.20220902.11
Page(s)	37-65
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2024. Published by Science Publishing Group

Keywords

AGPC Algorithmic Co-processor, Embedded PowerPC™440 Processor, FPGA, Model-Based Design (MBD), Nonlinear Model Predictive Control (NMPC), Nonlinear F-16 Aircraft, NMPC, Virtex-5 FX70T ML507 FPGA

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APA Style

Vincent Andrew Akpan, Dimitrios Chasapis, George Dimitriou Hassapis. (2022). FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC. American Journal of Embedded Systems and Applications, 9(2), 37-65. https://doi.org/10.11648/j.ajesa.20220902.11

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ACS Style

Vincent Andrew Akpan; Dimitrios Chasapis; George Dimitriou Hassapis. FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC. Am. J. Embed. Syst. Appl. 2022, 9(2), 37-65. doi: 10.11648/j.ajesa.20220902.11

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AMA Style

Vincent Andrew Akpan, Dimitrios Chasapis, George Dimitriou Hassapis. FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC. Am J Embed Syst Appl. 2022;9(2):37-65. doi: 10.11648/j.ajesa.20220902.11

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@article{10.11648/j.ajesa.20220902.11,
  author = {Vincent Andrew Akpan and Dimitrios Chasapis and George Dimitriou Hassapis},
  title = {FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC},
  journal = {American Journal of Embedded Systems and Applications},
  volume = {9},
  number = {2},
  pages = {37-65},
  doi = {10.11648/j.ajesa.20220902.11},
  url = {https://doi.org/10.11648/j.ajesa.20220902.11},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.ajesa.20220902.11},
  abstract = {The computational overload involved in the implementation of nonlinear model predictive control (NMPC) cannot be over-emphasized due to the double optimizations involved for the nonlinear model identification phase as well as the NMPC controller design phase. The computational burden becomes more time-critical for constrained multivariable control systems with relatively short sampling time. This paper presents a novel and comprehensive model-based design (MBD) approach for real-time closed-loop implementation of a version of NMPC referred here as adaptive generalized predictive control algorithmic co-processor (AGPC algorithmic co-processor) integrated with a well-designed embedded PowerPC™440 processor core on Virtex-5 FX70T ML507 FPGA (field programmable gate array) for the auto-pilot control of a nonlinear F-16 aircraft with a sampling time of 0.5 second. The result shows that the real-time closed-loop implementation of the neural network identification and the AGPC algorithms on the FPGA with embedded PowerPC™440 processor combined with an AGPC algorithmic co-processor at each sampling time is accomplished within 0.16502 microseconds (μs) when compared to the 6.1048 seconds obtained using Intel® Core™2 CPU personal computer for the control of the auto-pilot unit of a nonlinear F-16 aircraft. The demonstrated and validated model-based FPGA implementation techniques can be adapted and deployed for the real-time control of multivariable control systems having relatively short sampling time. The computation time and FPGA device utilization at each stage of the MBD implementation are also presented.},
 year = {2022}
}

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TY  - JOUR
T1  - FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC
AU  - Vincent Andrew Akpan
AU  - Dimitrios Chasapis
AU  - George Dimitriou Hassapis
Y1  - 2022/09/08
PY  - 2022
N1  - https://doi.org/10.11648/j.ajesa.20220902.11
DO  - 10.11648/j.ajesa.20220902.11
T2  - American Journal of Embedded Systems and Applications
JF  - American Journal of Embedded Systems and Applications
JO  - American Journal of Embedded Systems and Applications
SP  - 37
EP  - 65
PB  - Science Publishing Group
SN  - 2376-6085
UR  - https://doi.org/10.11648/j.ajesa.20220902.11
AB  - The computational overload involved in the implementation of nonlinear model predictive control (NMPC) cannot be over-emphasized due to the double optimizations involved for the nonlinear model identification phase as well as the NMPC controller design phase. The computational burden becomes more time-critical for constrained multivariable control systems with relatively short sampling time. This paper presents a novel and comprehensive model-based design (MBD) approach for real-time closed-loop implementation of a version of NMPC referred here as adaptive generalized predictive control algorithmic co-processor (AGPC algorithmic co-processor) integrated with a well-designed embedded PowerPC™440 processor core on Virtex-5 FX70T ML507 FPGA (field programmable gate array) for the auto-pilot control of a nonlinear F-16 aircraft with a sampling time of 0.5 second. The result shows that the real-time closed-loop implementation of the neural network identification and the AGPC algorithms on the FPGA with embedded PowerPC™440 processor combined with an AGPC algorithmic co-processor at each sampling time is accomplished within 0.16502 microseconds (μs) when compared to the 6.1048 seconds obtained using Intel® Core™2 CPU personal computer for the control of the auto-pilot unit of a nonlinear F-16 aircraft. The demonstrated and validated model-based FPGA implementation techniques can be adapted and deployed for the real-time control of multivariable control systems having relatively short sampling time. The computation time and FPGA device utilization at each stage of the MBD implementation are also presented.
VL  - 9
IS  - 2
ER  -

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Author Information

Vincent Andrew Akpan

Department of Biomedical Technology, The Federal University of Technology, Akure, Nigeria
Dimitrios Chasapis

Barcelona Supercomputing Center, Group Sonar, Barcelona, Spain
George Dimitriou Hassapis

Department of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Thessaloniki, Greece

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APA Style

Vincent Andrew Akpan, Dimitrios Chasapis, George Dimitriou Hassapis. (2022). FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC. American Journal of Embedded Systems and Applications, 9(2), 37-65. https://doi.org/10.11648/j.ajesa.20220902.11

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ACS Style

Vincent Andrew Akpan; Dimitrios Chasapis; George Dimitriou Hassapis. FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC. Am. J. Embed. Syst. Appl. 2022, 9(2), 37-65. doi: 10.11648/j.ajesa.20220902.11

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AMA Style

Vincent Andrew Akpan, Dimitrios Chasapis, George Dimitriou Hassapis. FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC. Am J Embed Syst Appl. 2022;9(2):37-65. doi: 10.11648/j.ajesa.20220902.11

Copy | Download

@article{10.11648/j.ajesa.20220902.11,
  author = {Vincent Andrew Akpan and Dimitrios Chasapis and George Dimitriou Hassapis},
  title = {FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC},
  journal = {American Journal of Embedded Systems and Applications},
  volume = {9},
  number = {2},
  pages = {37-65},
  doi = {10.11648/j.ajesa.20220902.11},
  url = {https://doi.org/10.11648/j.ajesa.20220902.11},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.ajesa.20220902.11},
  abstract = {The computational overload involved in the implementation of nonlinear model predictive control (NMPC) cannot be over-emphasized due to the double optimizations involved for the nonlinear model identification phase as well as the NMPC controller design phase. The computational burden becomes more time-critical for constrained multivariable control systems with relatively short sampling time. This paper presents a novel and comprehensive model-based design (MBD) approach for real-time closed-loop implementation of a version of NMPC referred here as adaptive generalized predictive control algorithmic co-processor (AGPC algorithmic co-processor) integrated with a well-designed embedded PowerPC™440 processor core on Virtex-5 FX70T ML507 FPGA (field programmable gate array) for the auto-pilot control of a nonlinear F-16 aircraft with a sampling time of 0.5 second. The result shows that the real-time closed-loop implementation of the neural network identification and the AGPC algorithms on the FPGA with embedded PowerPC™440 processor combined with an AGPC algorithmic co-processor at each sampling time is accomplished within 0.16502 microseconds (μs) when compared to the 6.1048 seconds obtained using Intel® Core™2 CPU personal computer for the control of the auto-pilot unit of a nonlinear F-16 aircraft. The demonstrated and validated model-based FPGA implementation techniques can be adapted and deployed for the real-time control of multivariable control systems having relatively short sampling time. The computation time and FPGA device utilization at each stage of the MBD implementation are also presented.},
 year = {2022}
}

Copy | Download

TY  - JOUR
T1  - FPGA Implementation of Neural Network-Based AGPC for Nonlinear F-16 Aircraft Auto-Pilot Control: Part 2 – Implementation of Embedded PowerPC™440 with AGPC
AU  - Vincent Andrew Akpan
AU  - Dimitrios Chasapis
AU  - George Dimitriou Hassapis
Y1  - 2022/09/08
PY  - 2022
N1  - https://doi.org/10.11648/j.ajesa.20220902.11
DO  - 10.11648/j.ajesa.20220902.11
T2  - American Journal of Embedded Systems and Applications
JF  - American Journal of Embedded Systems and Applications
JO  - American Journal of Embedded Systems and Applications
SP  - 37
EP  - 65
PB  - Science Publishing Group
SN  - 2376-6085
UR  - https://doi.org/10.11648/j.ajesa.20220902.11
AB  - The computational overload involved in the implementation of nonlinear model predictive control (NMPC) cannot be over-emphasized due to the double optimizations involved for the nonlinear model identification phase as well as the NMPC controller design phase. The computational burden becomes more time-critical for constrained multivariable control systems with relatively short sampling time. This paper presents a novel and comprehensive model-based design (MBD) approach for real-time closed-loop implementation of a version of NMPC referred here as adaptive generalized predictive control algorithmic co-processor (AGPC algorithmic co-processor) integrated with a well-designed embedded PowerPC™440 processor core on Virtex-5 FX70T ML507 FPGA (field programmable gate array) for the auto-pilot control of a nonlinear F-16 aircraft with a sampling time of 0.5 second. The result shows that the real-time closed-loop implementation of the neural network identification and the AGPC algorithms on the FPGA with embedded PowerPC™440 processor combined with an AGPC algorithmic co-processor at each sampling time is accomplished within 0.16502 microseconds (μs) when compared to the 6.1048 seconds obtained using Intel® Core™2 CPU personal computer for the control of the auto-pilot unit of a nonlinear F-16 aircraft. The demonstrated and validated model-based FPGA implementation techniques can be adapted and deployed for the real-time control of multivariable control systems having relatively short sampling time. The computation time and FPGA device utilization at each stage of the MBD implementation are also presented.
VL  - 9
IS  - 2
ER  -

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